1. Technical Field
This disclosure relates to integrated circuits, and more particularly, to clock gating in integrated circuits.
2. Description of the Related Art
Clock gating is a technique often used in integrated circuit (IC's) to achieve dynamic power savings. As some clock functional circuits may at times become idle during operation of an IC, power savings can be achieved by inhibiting the clock signal from being provided thereto. As such, dynamic power savings can be achieved, as the overall amount of switching is reduced in the IC when some circuits are not receiving a clock signal.
A wide variety of clock gating circuits are implemented in IC's today. Typical clock gating circuits include logic circuitry coupled to receive an enable signal and the clock signal (e.g., an AND gate), and circuitry for generating the enable signal. The circuitry for generating the enable signal may, for example, prevent the enable signal from changing states when the clock signal is in its active (e.g., high) state, which could adversely affect downstream functional circuitry. The enable generating circuitry for such clock gating circuits receives both the clock signal and its complement, and may also receive one or more high level enable signals. Such enable generating circuitry may ensure that the enable signal provided to the logic gate switched only when the clock signal is in its inactive (e.g., low) state.